Current electrical probe designs suffer from limitations in both design and manufacturing. Considerations include an increasing number of input/output channels, grounds, and power/electrical contact points and a decreasing array pitch size. Such limitations or concerns arise primarily because current probe designs require semiconductor solder pads or bumps to be mechanically engaged by a probe that continues travelling along a path substantially orthogonal to the surface of the semiconductor device even after initial contact to ensure a stable contact. This continuing travel is often called vertical overdrive and is used to ensure that each probe of a probe card contacts a corresponding contact point of the semiconductor device regardless of local or system variations (e.g., local non-planarity, semiconductor device tilting, and local height variations of pads). A prescribed amount of overdrive may be required (to meet a compliance requirement) to ensure that the probe card and its probes are able to absorb any of the local or device-wide variations to ensure that each probe has a stable contact with its target solder pad or bump.
With the grid array pitch size also becoming smaller, a space that may be used for an individual probe is also limited. It is extremely challenging to maintain an exact displacement while decreasing the size of a probe. This is because stresses to the probe may increase and exceed the probe material limits for yield strength and fatigue. For example, for a simple cantilever design, when a probe length is reduced by half, the maximum possible stress increases by a factor of four, for the same overdrive.
Reducing a required amount of overdrive is not a good option, given the above described local and device-wide variations. A long vertical probe may be a solution to address a large overdrive and high force requirement, but is not an ideal solution when considering signal integrity and cross talk requirements. Also, low probe resistance and high current carrying capacity may be requirements for the probe card. With limited space, a cross-section of the probe will also reduce, causing an increase in resistivity and reduction in current carrying capacity.
Other significant challenges pertain to manufacturing a probe with a sufficient overdrive capability to absorb local and device-wide variations. As the pitch between solder bumps or pads grows smaller, so does the real estate and the volume of space available for each individual probe. As the space allocated for each probe shrinks, it becomes increasingly difficult to construct a mechanical design that allows for large overdrives while maintaining stress levels at any point along the probe below the material maximum yield stress.